MSM62X42B
¡ Semiconductor
Reading and Writing of Registers S1 ~ W and Writing of 30-Second ADJ Bit
Registers S1 ~ W (Addresses 0 ~ C)
Reading and writing in the case of using HOLD bit
HOLD bit ¨ 1
READ BUSY bit
*
NO
BUSY bit = 0 ?
YES
HOLD bit ¨ 0
Write data into or
Read data from
registers S1~W
Idling time
HOLD bit ¨ 0
* In the inside of LSI, the CLEAR of BUSY bit is performed when
HOLD bit = 0, but, if the period of HOLD bit =0 is extermely
narrow as compared with the period of HOLD bit = 1, there is
some case that the CLEAR of BUSY bit delays so that the
BUSY bit can be cleared by sampling HOLD bit = 0 at approximate
16KHz. It is recommended to allow an idling time of 62ms or more.
58