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HM62256A View Datasheet(PDF) - Hitachi -> Renesas Electronics

Part Name
Description
Manufacturer
HM62256A
Hitachi
Hitachi -> Renesas Electronics Hitachi
HM62256A Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
HM62256A Series
HM62256A Series
AC Characteristics (Ta = 0 to +70ยฐC, VCC = 5 V ยฑ 10%, unless otherwise noted.)
Test Conditions
โ€ข Input pulse levels: 0.8 V to 2.4 V
โ€ข Input and output timing refernce levels: 1.5 V
โ€ข Input rise and fall times: 5 ns
โ€ข Output load: 1 TTL Gate + CL (100 pF)
(Including scope & jig)
Read Cycle
HM62256A-8 HM62256A-10 HM62256A-12 HM62256A-15
โ€”โ€”โ€”โ€”โ€”โ€“ โ€”โ€”โ€”โ€”โ€”โ€“ โ€”โ€”โ€”โ€”โ€”โ€“ โ€”โ€”โ€”โ€”โ€”โ€“
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Note
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Read cycle time
tRC
85 โ€” 100 โ€” 120 โ€” 150 โ€” ns
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Address access time tAA
โ€” 85 โ€” 100 โ€” 120 โ€” 150 ns
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Chip select
access time
tACS
โ€” 85 โ€” 100 โ€” 120 โ€” 150 ns
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Output enable to
output valid
tOE
โ€” 45 โ€” 50 โ€” 60 โ€” 70 ns
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Chip selection to
output in low-Z
tCLZ
10 โ€” 10 โ€” 10 โ€” 10 โ€” ns 2
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Output enable to
output in low-Z
tOLZ
5
โ€”5
โ€”5
โ€”5
โ€” ns 2
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Chip deselection to
tCHZ
0
30 0
35 0
40 0
50 ns
1, 2
output in high-Z
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Output disable to
output in high-Z
tOHZ
0
30 0
35 0
40 0
50 ns
1, 2
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
Output hold from
address change
tOH
5
โ€” 10 โ€” 10 โ€” 10 โ€”
ns
โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€”โ€“
6

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