Signal Descriptions
Table 3. MCF5207/8 Signal Information and Muxing (continued)
Signal Name
PSTCLK
BKPT
DSI
DSO
DDATA[3:0]
PST[3:0]
ALLPST
GPIO
โ
โ
โ
โ
โ
โ
โ
Alternate 1
TCLK2
TMS2
TDI2
TDO
โ
โ
โ
MCF5207
Alternate 2 Dir.1
144
LQFP
MCF5207
144
MAPBGA
MCF5208
160
QFP
โ
O
64
M7
70
โ
I
75
L12
83
โ
I
77
H9
85
โ
O
69
M9
75
โ
O
โ
K9, L9, M11,
โ
M8
โ
O
โ
L11, L8,
โ
K10, K8
โ
O
67
โ
73
MCF5208
196
MAPBGA
P9
M14
K12
M12
P11, N11,
M11, P10
N10, M10,
L10, L9
โ
TEST6
โ
PLL_TEST
โ
Test
โ
โ
I
109
โ
โ
C12
โ
โ
I
โ
โ
โ
M13
Power Supplies
EVDD
โ
โ
โ
1, 63, 66, 72, E5โE6, F5, 2, 9, 69, 72, E5โE7, F5,
81, 87, 125 G8โG9, 80, 89, 95, F6, G5, H10,
H7โH8
131
J9, J10,
K8โK10,
K13, M9
IVDD
โ
โ
โ
30, 68, 84, D4, D8, H4, 36, 74, 92, J12, D4,
113, 143
H11, J9
121, 159 D11, H11,
L4, L11,
PLL_VDD
โ
โ
โ
86
H12
94
H13
SD_VDD
โ
โ
โ
3, 17, 33, 35, E7โE8, F8, 11, 39, 41, E8โE10, F9,
61, 89, 110, G5, H5โH6, 67, 97, 118, F10, G10,
123
J3
129
H5, J5, J6,
K5โK7, L2
VSS
โ
โ
โ
2, 16, 36, 62, D10, F6โF7, 1, 10, 42, 68, A1, A14,
65, 73, 88, G6โG7 71, 81, 96, F7โF8,
111, 124
117, 119, G6โG9,
130
H6โH9,
J7โJ8, L13,
M2, N9, P1,
P14
PLL_VSS
โ
โ
โ
85
โ
93
H12
NOTES:
1 Refers to pinโs primary function.
2 Pull-up enabled internally on this signal for this mode.
3 Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating
the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
4 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate
functions.
MCF5208 ColdFireยฎ Microprocessor Data Sheet, Rev. 0.5
Freescale Semiconductor
Preliminary
7