3.3.21 ESMRAMCâExtended System Management RAM Control Register
(Device 0) ......................................................................................3-29
3.3.22 RPSâSDRAM Row Page Size Register (Device 0)......................3-30
3.3.23 SDRAMCâSDRAM Control Register (Device 0) ..........................3-30
3.3.24 PGPOLâPaging Policy Register (Device 0) .................................3-32
3.3.25 PMCRâPower Management Control Register (Device 0) ............3-33
3.3.26 SCRRâSuspend CBR Refresh Rate Register (Device 0) ............3-34
3.3.27 EAPâError Address Pointer Register (Device 0)..........................3-34
3.3.28 ERRCMDâError Command Register (Device 0) ..........................3-35
3.3.29 ERRSTSâError Status Register (Device 0)..................................3-36
3.3.30 ACAPIDâAGP Capability Identifier Register (Device 0) ...............3-37
3.3.31 AGPSTATâAGP Status Register (Device 0) ................................3-37
3.3.32 AGPCMDâAGP Command Register (Device 0)...........................3-38
3.3.33 AGPCTRLâAGP Control Register (Device 0) ..............................3-39
3.3.34 APSIZEâAperture Size Register (Device 0) .................................3-40
3.3.35 ATTBASEâAperture Translation Table Base Register
(Device 0) ......................................................................................3-40
3.3.36 MBFSâMemory Buffer Frequency Select Register
(Device 0) ......................................................................................3-41
3.3.37 BSPADâBIOS Scratch Pad Register (Device 0) ..........................3-43
3.3.38 DWTCâDRAM Write Thermal Throttling Control Register
(Device 0) ......................................................................................3-43
3.3.39 DRTCâDRAM Read Thermal Throttling Control Register
(Device 0) ......................................................................................3-44
3.3.40 BUFFCâBuffer Control Register (Device 0) .................................3-45
3.4 PCI-to-PCI Bridge Registers (Device 1) .....................................................3-46
3.4.1 VID1âVendor Identification Register (Device 1)...........................3-47
3.4.2 DID1âDevice Identification Register (Device 1) ...........................3-47
3.4.3 PCICMD1âPCI-to-PCI Command Register (Device 1) ................3-48
3.4.4 PCISTS1âPCI-to-PCI Status Register (Device 1) ........................3-49
3.4.5 RID1âRevision Identification Register (Device 1) ........................3-49
3.4.6 SUBC1âSub-Class Code Register (Device 1) .............................3-50
3.4.7 BCC1âBase Class Code Register (Device 1) ..............................3-50
3.4.8 MLT1âMaster Latency Timer Register (Device 1)........................3-50
3.4.9 HDR1âHeader Type Register (Device 1) .....................................3-51
3.4.10 PBUSNâPrimary Bus Number Register (Device 1)......................3-51
3.4.11 SBUSNâSecondary Bus Number Register (Device 1) .................3-51
3.4.12 SUBUSNâSubordinate Bus Number Register (Device 1) ............3-52
3.4.13 SMLTâSecondary Master Latency Timer Register
(Device 1) ......................................................................................3-52
3.4.14 IOBASEâI/O Base Address Register (Device 1) ..........................3-52
3.4.15 IOLIMITâI/O Limit Address Register (Device 1) ...........................3-52
3.4.16 SSTSâSecondary PCI-to-PCI Status Register (Device 1) ...........3-53
3.4.17 MBASEâMemory Base Address Register (Device 1)...................3-54
3.4.18 MLIMITâMemory Limit Address Register (Device 1)....................3-54
3.4.19 PMBASEâPrefetchable Memory Base Address Register
(Device 1) ......................................................................................3-55
3.4.20 PMLIMITâPrefetchable Memory Limit Address Register
(Device 1) ......................................................................................3-55
3.4.21 BCTRLâPCI-to-PCI Bridge Control Register (Device 1) ..............3-56
vi
82443GX Host Bridge Datasheet