Features
• EE Programmable 524,288 x 1- and 1,048,576 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
• In-System Programmable via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX® Devices, Lucent ORCA®
FPGAs, Xilinx XC3000, XC4000, XC5200, SPARTAN® and Virtex® FPGAs
• Cascadable Read Back to Support Additional Configurations or Future
Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in PLCC Package (Pin-compatible Across Product Family)
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V ± 10% LV and 5V ± 5% C Versions
• System-friendly READY Pin
• Low-power Standby Mode
Description
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA
Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-
figuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged
in the popular 20-pin PLCC. The AT17 Series family uses a simple serial-access pro-
cedure to configure one or more FPGA devices. The AT17 Series organization
supplies enough memory to configure one or multiple smaller FPGAs. The user can
select the polarity of the reset function by programming four EEPROM bytes. These
devices also support a write protection mode and a system-friendly READY pin, which
signifies a “good” power level to the FPGA and can be used to ensure reliable system
power-up.
The AT17 Configurator Series can be programmed with industr y-standard
programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
FPGA
Configuration
EEPROM
Memory
512K and 1M
AT17C512
AT17LV512
AT17C010
AT17LV010
Pin Configurations
20 PLCC
CLK 4
WP1 5
RESET/OE 6
WP2 7
CE 8
18 NC
17 SER_EN
16 NC
15 READY
14 CEO (A2)
8 LAP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
8 PDIP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
Rev. 0944D–06/01
1