Integrated Device Technology
6. Pinning information
6.1 Pinning
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
WHUPLQDO
LQGH[DUHD
&/.3
&/.1
0'63
0'61
70
$/,*13
$/,*11
/'>@3
/'>@1
/'>@3
/'>@1
9'''
/'>@3
/'>@1
/'>@3
/'>@1
/'>@3
/'>@1
'$&'*
5(6(7B1
6&6B1
6&/.
6',2
6'2
,2
,2
/'>@1
/'>@3
/'>@1
/'>@3
9'''
/'>@1
/'>@3
/'>@1
/'>@3
/'>@1
/'>@3
DDD
Fig 2. Pin configuration
7UDQVSDUHQWWRSYLHZ
6.2 Pin description
Table 2.
Symbol
CLKP
CLKN
MDSP
MDSN
TM
ALIGNP
ALIGNN
LD[15]P
LD[15]N
Pin description
Pin
Type[1]
1
I
2
I
3
IO
4
IO
5
I
6
I
7
I
8
I
9
I
Description
DAC clock positive input
DAC clock negative input
multi-device synchronization positive signal
multi-device synchronization negative signal
Test mode selection (connect to GND)
positive input for data alignment
negative input for data alignment
LVDS positive input bit 15[2]
LVDS negative input bit 15[2]
DAC1617D1G0 3
Preliminary data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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