EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
b7
b0
SRWD 0 0 0 BP1 BP0 WEL BUSY
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
BUSY Bit
Table 3: Status Register Format
Status Register
Content
Memory Contents
BP1 Bit BP0 Bit Protected Area
0
0 None
Unprotected Area
All blocks* (4 blocks: 0, 1, 2. & 3)
0
1 Upper quarter (Block 3)
Lower three-quarters (3 blocks: 0 to 2)
1
0 Upper half (2 blocks: 2 and 3)
Lower half (Two blocks: 0 and 1)
1
1 All blocks (4 blocks: 0, 1, 2. & 3)
None
* The device is ready to accept a Chip Erase instruction provided that both Block Protects
(BP1 and BP0) are set to “0”.
Table 4: Protected Area Sizes
This specification is subject to change without further notice. (11.08.2004 V1.0)
Page 7 of 30