M36W0R6050T1
M36W0R6050B1
64 Mbit (4 Mb ร16, Multiple Bank, Burst) Flash memory
and 32 Mbit (2 Mb ร16) PSRAM, multi-chip package
Features
โ Multi-Chip Package
โ 1 die of 64 Mbit (4 Mb ร 16) Flash memory
โ 1 die of 32 Mbit (2 Mb ร 16) Pseudo SRAM
โ Supply voltage
โ VDDF = VDDP = VDDQF = 1.7 V to 1.95 V
โ Low power consumption
โ Electronic signature
โ Manufacturer Code: 20h
โ Device code (top flash configuration),
M36W0R6050T1: 8810h
โ Device code (bottom flash configuration),
M36W0R6050B1: 8811h
โ Package
โ ECOPACKยฎ
Flash memory
โ Programming time
โ 8 ยตs by Word typical for Fast Factory
Program
โ Double/Quadruple Word Program option
โ Enhanced Factory Program options
โ Memory blocks
โ Multiple Bank memory array: 4 Mbit Banks
โ Parameter Blocks (Top or Bottom location)
โ Synchronous / Asynchronous Read
โ Synchronous Burst Read mode: 66 MHz
โ Asynchronous/ Synchronous Page Read
mode
โ Random Access: 70 ns
โ Dual operations
โ Program Erase in one Bank while Read in
others
โ No delay between Read and Write
operations
FBGA
Stacked TFBGA88
(ZA)
โ Block locking
โ All blocks locked at Power-up
โ Any combination of blocks can be locked
โ WPF for Block Lock-Down
โ Security
โ 128-bit user programmable OTP cells
โ 64-bit unique device number
โ Common Flash Interface (CFI)
โ 100 000 program/erase cycles per block
PSRAM
โ Access time: 70 ns
โ Asynchronous Page Read
โ Page size: 8 words
โ First access within page: 70 ns
โ Subsequent read within page: 20 ns
โ Three Power-down modes
โ Deep Power-Down
โ Partial Array Refresh of 4 Mbits
โ Partial Array Refresh of 8 Mbits
January 2007
1
1/22
www.st.com
1