MBM29BS32LF-18 View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

MBM29BS32LF-18

BURST MODE FLASH MEMORY CMOS 32M (2M × 16) BIT

Spansion Inc. 

MBM29BS/BT32LF-18/25

MBM29BS/BT32LF Command Definitions Table

Command

Sequence

Bus First Bus

Write Write Cycle

Cycles

Req’d Addr. Data

Second Write Third Write

Cycle

Cycle

Addr. Data Addr. Data

Fourth Write

Cycle

Addr. Data

Fifth Write

Cycle

Addr. Data

Sixth Write

Cycle

Addr. Data

Asynchronous

Read / Reset

1 XXXh F0h RA RD — — — — — — — —

Asynchronous

Read / Reset

3 555h AAh 2AAh 55h 555h F0h RA RD — — — —

Autoselect

3

555h

AAh

2AAh

55h

(BA)

555h

90h

—

—

—

—

—

—

Program

4 555h AAh 2AAh 55h 555h A0h PA PD — — — —

Chip Erase

6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h

Sector Erase

6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h

Erase Suspend

1 BA B0h — — — — — — — — — —

Erase Resume

1 BA 30h — — — — — — — — — —

Fast Program

2 XXXh A0 PA PD

Set to Fast Mode

3 555h AAh 2AAh 55h 555h 20h — — — — — —

Reset from Fast

Mode *1

2 BA 90h XXXh F0h*2 — — — — — — — —

Sector Lock/Unlock

(Sector Command 3 XXXh 60h XXXh 60h SLA 60h — — — — — —

Locking)

Set Burst Mode

Configuration

Register

3

555h

AAh

2AAh

55h

(CR)

555h

C0h

—

—

—

—

—

—

Query

1

(BA)

55h

98h

—

—

—

—

—

—

—

—

—

—

Legend:

RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Address latches on the rising edge of AVD pulse or

active CLK edge while AVD=VIL or falling edge of write pulse while AVD=VIL

SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14 and A13 will uniquely

select any sector.

BA = Bank Address. Address setted by A20, A19 will select Bank A, Bank B, Bank C and Bank D.

SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for

locked.

RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data latches on the rising edge of write pulse.

CR = Configuration Register address bits A19 to A12.

*1: This command is valid during Fast Mode.

*2: The data “00h” is also acceptable.

Notes: • Address bits A20 to A11 = X = “H” or “L” for all address commands except for PA, SA, BA.

• Bus operations are defined in “MBM29BS/BT32LF User Bus Operations Table” (in sDEVICE BUS

OPERATIONS).

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

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