Philips Semiconductors
Wideband code division multiple access
frequency division duplex zero IF receiver
Objective specification
UAA3580
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
Fractional-N synthesizer; fCLKPLL
=
fr
ef
×
N------+-----2K----A----F---C--
where KAFC
=
25----31---12-- + A---2--F-2---1C---
N
integer divider ratio
KAFC
fractional divider ratio
Integrated CLKPLL VCO; pin CPCLKO
−
9
0.4512 −
fVCO
CLKPLL frequency
GVCO
VCO gain
Vtune
tuning voltage
Output CLKPLL buffer; pin UMTSCLKO
VCPCLKO = 0 to 3.3 V
VCPCLKO = 1.3 V
100 −
12
15
0.4
−
fUMTSCLKO
N
Φn
Vo(p-p)
frequency range
divider ratio
close-in-phase noise
phase noise
output voltage (peak-to-peak
value)
at 2 kHz offset for
30.72 MHz
at 3.84 MHz offset for
30.72 MHz
RL = 10 kΩ
15.36
2
−
30.72
4
−
−
−
1
−
Low noise crystal amplifier; pin REFIN
fREF
Vi(REF)(rms)
Ri(REF)
Ci(REF)
reference frequency
input voltage (RMS value)
input resistance
input capacitance
fREF = 26 MHz
fREF = 26 MHz
13
−
50
−
−
tbf
−
tbf
MAX.
UNIT
−
0.4532
140
23
VCCA − 0.4
MHz
MHz/V
V
61.44
8
−90
−110
−
MHz
dBc/Hz
dBc/Hz
V
26
MHz
400
mV
−
kΩ
−
pF
2002 Oct 30
17