µPD6379, 6379A, 6379L, 6379AL
• If the clock is also supplied to CLK while data is not sampled (refer to Fig. 4-1), make sure that the changing
timing of LRCK coincides with the falling edge (point A) of CLK after the LSB has been input.
Fig. 4-1 Input Timing Chart (1)
A
CLK
LSB
SI
16
Invalid
LRCK
A
1 sample data period
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Invalid
MSB
1234
• If the clock is supplied to CLK only while data is sampled (refer to Fig. 4-2), set the changing timing of LRCK
in between the falling edge (point A) of CLK after the LSB has been input and the start of inputting the next
MSB (point B) (points A and B are included).
Fig. 4-2 Input Timing Chart (2)
A
CLK
LSB
SI
16 Invalid
B
A
1 sample data period
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Invalid
B
MSB
1234
LRCK
Changing period of LRCK
Changing period of LRCK
Data Sheet S11588EJ4V0DS00
11