I2C Gamma and VCOM Buffer with EEPROM
S0/S1
tHD
LD
VIL
VIH
VIL
tSU
VIH
GM1–10
Figure 2. GM1–10 Settling Timing Diagram
tSET-G
GM1–GM10
ILOAD
4 TAU SETTLED
100pF
S0/S1
(LD = VCC)
GM1–GM10
VIH
VIL
tSEL
OUTPUT 10% SETTLED
Figure 3. Input Pin to Output Change Timing Diagram
GM1–GM10
100pF
SDA
tBUF
tLOW
tR
tF
tHD:STA
tSP
SCL
STOP
START
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
REPEATED
START
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 4. I2C Timing Diagram
6 _______________________________________________________________________________________
tSU:STO