FM24CL64B
AC Switching Characteristics
Over the Operating Range
Parameter [6]
Cypress
Alt.
Parameter Parameter
Description
fSCL[7]
SCL clock frequency
tSU; STA
Start condition setup for repeated Start
tHD;STA
Start condition hold time
tLOW
Clock LOW period
tHIGH
Clock HIGH period
tSU;DAT
tSU;DATA Data in setup
tHD;DAT
tHD;DATA Data in hold
tDH
tR[8]
tr
tF[8]
tf
Data output hold (from SCL @ VIL)
Input rise time
Input fall time
tSU;STO
STOP condition setup
tAA
tVD;DATA SCL LOW to SDA Data Out Valid
tBUF
Bus free before new transmission
tSP
Noise suppression time constant on SCL, SDA
Min Max Min Max Min Max Unit
โ 0.1 โ 0.4 โ 1.0 MHz
4.7 โ 0.6 โ 0.25 โ ๏ญs
4.0 โ 0.6 โ 0.25 โ ๏ญs
4.7 โ 1.3 โ 0.6 โ ๏ญs
4.0 โ 0.6 โ 0.4 โ ๏ญs
250 โ 100 โ 100 โ ns
0
โ
0
โ
0
โ ns
0
โ
0
โ
0
โ ns
โ 1000 โ 300 โ 300 ns
โ 300 โ 300 โ 100 ns
4.0 โ 0.6 โ 0.25 โ ๏ญs
โ
3
โ 0.9 โ 0.55 ๏ญs
4.7 โ 1.3 โ 0.5 โ ๏ญs
โ 50 โ 50 โ 50 ns
Figure 14. Read Bus Timing Diagram
tR
` tF
tHIGH
tLOW
tSP
tSP
SCL
tSU:SDA
tBUF
SDA
1/fSCL
tHD:DAT
tSU:DAT
Start
Stop Start
tAA
tDH
Acknowledge
Figure 15. Write Bus Timing Diagram
SCL
SDA
tSU:STO
tHD:DAT
tHD:STA
tSU:DAT
tAA
Start
Stop Start
Acknowledge
Notes
6. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD(typ), and output loading of the specified
IOL and load capacitance shown in Figure 13.
7. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max).
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-84458 Rev. *I
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