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S-25A080A View Datasheet(PDF) - Seiko Instruments Inc

Part Name
Description
Manufacturer
S-25A080A Datasheet PDF : 31 Pages
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125ยฐC OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
S-25A080A/160A/320A
Rev.1.0_00
Table 13
Item
โˆ’40ยฐC to +85ยฐC
Symbol VCC = 2.5 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 4.5 V to 5.5 V Unit
Min.
Max.
Min.
Max.
Min.
Max.
SCK clock frequency
fSCK
โˆ’
4.0
โˆ’
5.0
โˆ’
7.0
MHz
CS setup time during CS
falling
tCSS.CL
90
โˆ’
80
โˆ’
60
โˆ’
ns
CS setup time during CS
rising
tCSS.CH
90
โˆ’
80
โˆ’
60
โˆ’
ns
CS deselect time
tCDS
150
โˆ’
120
โˆ’
100
โˆ’
ns
CS hold time during CS falling tCSH.CL
90
โˆ’
80
โˆ’
60
โˆ’
ns
CS hold time during CS rising
tCSH.CH
90
โˆ’
80
โˆ’
60
โˆ’
ns
SCK clock time โ€œHโ€ *1
SCK clock time โ€œLโ€ *1
Rising time of SCK clock *2
Falling time of SCK clock *2
tHIGH
115
โˆ’
90
โˆ’
60
โˆ’
ns
tLOW
115
โˆ’
90
โˆ’
60
โˆ’
ns
tRSK
โˆ’
1
โˆ’
1
โˆ’
1
ยตs
tFSK
โˆ’
1
โˆ’
1
โˆ’
1
ยตs
SI data input setup time
tDS
20
โˆ’
20
โˆ’
20
โˆ’
ns
SI data input hold time
tDH
30
โˆ’
30
โˆ’
30
โˆ’
ns
SCK โ€œLโ€ hold time
during HOLD rising
tSKH.HH
70
โˆ’
60
โˆ’
40
โˆ’
ns
SCL โ€œLโ€ hold time
during HOLD falling
tSKH.HL
40
โˆ’
40
โˆ’
30
โˆ’
ns
SCK โ€œLโ€ setup time
during HOLD falling
tSKS.HL
0
โˆ’
0
โˆ’
0
โˆ’
ns
SCK โ€œLโ€ setup time
during HOLD rising
tSKS.HH
0
โˆ’
0
โˆ’
0
Disable time of SO output *2
tOZ
โˆ’
100
โˆ’
100
โˆ’
Delay time of SO output
tOD
โˆ’
110
โˆ’
85
โˆ’
Hold time of SO output
Rising time of SO output *2
Falling time of SO output *2
tOH
0
โˆ’
0
โˆ’
0
tRO
โˆ’
80
โˆ’
50
โˆ’
tFO
โˆ’
80
โˆ’
50
โˆ’
Disable time of SO output
during HOLD falling *2
tOZ.HL
โˆ’
100
โˆ’
100
โˆ’
โˆ’
ns
70
ns
55
ns
โˆ’
ns
40
ns
40
ns
70
ns
Delay time of SO output
during HOLD rising *2
tOD.HH
โˆ’
80
โˆ’
75
โˆ’
55
ns
WP setup time
tWS1
0
โˆ’
0
โˆ’
0
โˆ’
ns
WP hold time
tWH1
0
โˆ’
0
โˆ’
0
โˆ’
ns
WP release / setup time
tWS2
0
โˆ’
0
โˆ’
0
โˆ’
ns
WP release / hold time
tWH2
150
โˆ’
150
โˆ’
100
โˆ’
ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1/fSCK ยตs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1/fSCK) = tLOW (Min.) + tHIGH (Min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
8
Seiko Instruments Inc.

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