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AD9540 Datasheet - ADI

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Description
MFG CO.
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PRODUCT OVERVIEW
The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phase-locked loop) circuitry, including a flexible 200 MHz phase frequency detector and a digitally controlled charge pump current. The device also provides a low jitter, 655 MHz CMLmode, PECL-compliant output driver with programmable slew rates. External VCO rates up to 2.7 GHz are supported.

FEATURES
   Excellent intrinsic jitter performance
   200 MHz phase frequency detector inputs
   655 MHz programmable input dividers for the phase
      frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable)
   Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
   8 programmable phase/frequency profiles
   400 MSPS internal DDS clock speed
   48-bit frequency tuning word resolution
   14-bit programmable phase offset
   1.8 V supply for device operation
   3.3 V supply for I/O, CML driver, and charge pump output
   Software controlled power-down
   48-lead LFCSP_VQ package
   Programmable charge pump current (up to 4 mA)
   Dual-mode PLL lock detect
   655 MHz CML-mode PECL-compliant output driver

APPLICATIONS
   Clocking high performance data converters
   Base station clocking applications
   Network (SONET/SDH) clocking
   Gigabit Ethernet (GbE) clocking
   Instrumentation clocking circuits
   Agile LO frequency synthesis
   Automotive radar
   FM chirp source for radar and scanning systems
   Test and measurement equipment
   Acousto-optic device drivers

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