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XA-C3 Datasheet - Philips

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MFG CO.
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GENERAL DESCRIPTION
The XA–C3 is a member of the Philips XA (eXtended Architecture) family of high–performance 16–bit single–chip microcontrollers. The XA–C3 combines an array of standard peripherals together with a PeliCAN CAN 2.0B engine and unique ”Message Management” hardware to provide integrated support for most CAN Transport Layer (CTL) protocols such as DeviceNet, CANopen and OSEK. For additional details, refer to the XA-C3 Overview on page 35.

The XA architecture supports:
• Easy 16-bit migration from the 80C51 architecture.
• 16–bit fully static CPU with 24–bit addressed PROGRAM and DATA spaces.
• Twenty–one 16–bit CPU core registers capable of all arithmetic and logic operations while serving as memory pointers.
• An enhanced orthogonal instruction set tailored for high–level support of the C language.
• Multi–tasking and direct real–time executive support.
• Low–power operation intrinsic to the XA architecture includes Power–Down and Idle modes.

FEATURES IN COMMON WITH XA-G3
• Pin–compatibility (CAN RxD and CAN TxD use the XA-G3 NC pins).
• 32K bytes of on–chip EPROM PROGRAM memory (see Table 1).
• 44–pin PLCC (Figure 1 and Table 2) and 44–pin LQFP (Figure 2 and Table 3) packages.
• Commercial (0 to 70oC) and Industrial (–40 to 85oC) ranges.
• Supports off–chip addressing of PROGRAM and DATA memory up to 1 megabyte each (20 address lines).
• Three standard counter/timers (T0, T1, and T2) with enhancements such as Auto Reload for PWM outputs.
• UART–0 with enhancements such as separate Rx and Tx interrupts, Break Detection, and Automatic Address Recognition.
• Watchdog with a secure WFEED1 / WFEED2 sequence.
• Four 8–bit I/O ports with 4 programmable output configurations per pin.

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Part Name
Description
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MFG CO.
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