Multimedia ICs
2. Master mode, doubled clock mode
Encoder master (pin 33 = H)
Internal clock = 2∗ input clock (pin 53 = H)
VCLK (pin53)
Internal clock
(BCLK)
Input data
Output data
(HSY, VSY)
BU1425AK / BU1425AKV
Tds2
Fig.12
∗ In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, fol-
lowing the rise of the RSTB pin (pin 52).
Table 12
Parameter
Data setup time 2
Symbol
Min.
Typ.
Max.
Tds2
10
—
—
3. Slave mode, ∗1 clock mode
Encoder slave (pin 33 = H)
Internal clock = input clock (pin 53 = H)
VCLK (pin53)
Internal clock
(BCLK)
Input data
Input data
(HSY, VSY)
Tsh1 Tsd1
Fig.13
Tds3S Tds3H
19