DS1821 View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
Manufacturer
DS1821 Datasheet PDF : 18 Pages
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DS1821
Figure 9 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15 μs for a read time slot.
Figure 10 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible
and by locating the master sample time during read time slots towards the end of the 15 μs period.
READ/WRITE TIME SLOT TIMING DIAGRAM Figure 8
LINE TYPE LEGEND (Figure 8, Figure 9 and Figure 10)
Bus master pulling low
DS1821 pulling low
Resistor pullup
START
OF SLOT
MASTER WRITE “0” SLOT
VDD
1-WIRE BUS
GND
15 μs
60 μs < TX “0” < 120
DS1821 samples
MIN
TYP
MAX
15 μs
30 μs
START
OF SLOT
MASTER WRITE “1” SLOT
∞ 1 μs < TREC <
> 1 μs
15 μs
DS1821 samples
MIN
TYP
MAX
15 μs
30 μs
VDD
1-WIRE BUS
GND
> 1 μs
MASTER READ “0” SLOT
15 μs
Master samples
45 μs
> 1 μs
MASTER READ “1” SLOT
∞ 1 μs < TREC <
15 μs
Master samples
DETAILED MASTER READ 1 TIMING Figure 9
VDD
1-WIRE BUS
GND
TINT > 1 μs
TRC
15 μs
VIH of Master
Master samples
RECOMMENDED MASTER READ 1 TIMING Figure 10
VDD
1-WIRE BUS
VIH of Master
GND
TINT = TRC =
small small
15 μs
Master samples
13 of 18
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