UPD7225GB-3B7 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD7225GB-3B7

PROGRAMMABLE LCD CONTROLLER/DRIVER

NEC => Renesas Technology 

µPD7225

1. PIN FUNCTIONS

1.1 SI (Serial Input)……Input

This pin is used for inputting serial data (commands/data). Data to be displayed as well as 19 deffernet

commands for controlling the operation of the µPD7225 can be input to this pin.

1.2 /SCK (Serial Clock)……Input

This pin is used for inputting the shift clock for serial data (SI input). The content of the SI input is read into the

serial register at the rising edge of this clock one bit at a time. /SCK input is effective when /CS = 0 and /BUSY = 1.

If /BUSY = 0, this input is ignored. If /CS = 1, this signal is ignored regardless of the /BUSY status.

1.3 C, /D (Command/Data)……Input

This input indicates whether the signal input from the SI pin is a command or data. A low level indicates data; a

high level indicates a command.

1.4 /BUSY……Tri-state output

This is an active-low output pin that is used to control serial data input disable/enable. A low level disables serial

data input; a high level enables serial data input. This pin becomes high impedance when /CS = 1.

1.5 /CS (Chip Select)……Input

When /CS is changed from high level to low level, the SCK counter in the µPD7225 is cleared and serial data

input is enabled. At the same time, the data pointer is initialized to address 0. When /CS is set to high level after

serial data is input, the contents of the data memory are transferred to the display latch and displayed on the LCD.

1.6 /SYNC (SYNChronous)……Input/Output

The /SYNC pin is used to make a wired-OR connection when the common pins are shared or when blinking

operation is synchronized in a multi-chip configuration.

When the µPD7225 is reset (/RESET = 0), the /SYNC pin outputs the clock frequency (fCL) divided by four (refer to

Figure 1-1), and synchronizes the system clock (fCL/4) of the µPD7225. When the reset is released (/RESET =1), the

display timing of each µPD7225 is synchronized with the common drive signal timing shown in Figure 1-2.

Figure 1-1. /SYNC Pin Status During Reset (/RESET = 0)

fCL

/SYNC

Data Sheet S14308EJ6V0DS00

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