AM85C30-8PC View Datasheet(PDF) - Advanced Micro Devices

Part Name

Description

Manufacturer

AM85C30-8PC

Enhanced Serial Communications Controller

Advanced Micro Devices 

AMD

D/C

High

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

“Point High”

Code In WR0:

Either Way

Not True

Not True

Not True

Not True

Not True

Not True

Not True

Not True

True

True

True

True

True

True

True

True

Table 2. Register Addressing

D2, D1, D0

In WR0:

X

X

X

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

Write

Register

Data

0

1

2

3

4

5

6

7

Data

9

10

11

12

13

14

15

Read

Register

Data

0

1

2

3

(0)

(1)

(2)

(3)

Data

–

10

(15)

12

13

(10)

15

Read Registers

The ESCC contains eight Read registers [actually nine,

counting the receive buffer (RR8) in each channel]. Four

of these may be read to obtain status information (RR0,

RR1, RR10, and RR15). Two registers (RR12 and

RR13) may be read to learn the baud rate generator

time constant. RR2 contains either the unmodified inter-

rupt vector (Channel A) or the vector modified by status

information (Channel B). RR3 contains the Interrupt

Pending (IP) bits (Channel A). In addition, if bit D2 of

WR15 is set, RR6 and RR7 are available for providing

frame status from the 10 × 19 bit Frame Status FIFO.

Figure 8 shows the formats for each Read register.

The status bits of RR0 and RR1 are carefully grouped to

simplify status monitoring, for example, when the inter-

rupt vector indicates a Special Receive Condition

interrupt, all the appropriate error bits can be

read from a single register (RR1). Please refer to

Am85C30 Technical Manual for detailed descriptions of

the read registers.

Write Registers

The ESCC contains 15 Write registers (16 counting

WR8, the transmit buffer) in each channel. These Write

registers are programmed separately to configure the

functional “personality” of the channels. Two registers

(WR2 and WR9) are shared by the two channels that

can be accessed through either of them. WR2 contains

the interrupt vector for both channels, while WR9 con-

tains the interrupt control bits. In addition, if bit D0 of

WR15 is set, Write Register 7 prime (WR7′) is available

for programming additional SDLC/HDLC enhance-

ments. When bit D0 of WR15 is set, executing a write to

WR7 actually writes to WR7′ to further enhance the

functional “personality” of each channel. Figure 8 shows

the format of each Write register.

18

Am85C30

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