MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Block Diagram
x4 Configuration
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 2048
x 4 bit
Row decoder
Memory array
Bank 1
4096 x 2048
x 4 bit
Row decoder
Memory array
Bank 2
4096 x 2048
x 4 bit
Row decoder
Memory array
Bank 3
4096 x 2048
x 4 bit
Input buffer Output buffer
I/O1-I/O4
Control logic & timing generator
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
5