AD9772A View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9772A Datasheet PDF : 32 Pages
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AD9772A–SPECIFICATIONS
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless
otherwise noted.)
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current*
Logic “0” Current
Input Capacitance
2.1
3
0
–10
–10
5
V
0.9
V
+10
µA
+10
µA
pF
CLOCK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
0
3
V
0.75
1.5
2.25
V
0.5
1.5
V
PLL CLOCK ENABLED—FIGURE 1a
Input Setup Time (tS), TA = 25°C
0.5
Input Hold Time (tH), TA = 25°C
1.0
Latch Pulsewidth (tLPW), TA = 25°C
1.5
PLL CLOCK DISABLED—FIGURE 1b
Input Setup Time (tS), TA = 25°C
–1.2
Input Hold Time (tH), TA = 25°C
3.2
Latch Pulsewidth (tLPW), TA = 25°C
1.5
CLK/PLLLOCK Delay (tOD), TA = 25°C
2.8
PLLLOCK (VOH), TA = 25°C
3.0
PLLLOCK (VOL), TA = 25°C
*MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 µA.
Specifications subject to change without notice.
ns
ns
ns
ns
ns
ns
3.2
ns
V
0.3
V
DB0–DB13
CLK+ – CLK–
tS
tH
tLPW
DB0–DB13
PLLLOCK
CLK+ – CLK–
tH
tS
tOD
tLPW
IOUTA
OR
IOUTB
tPD
tST
0.025%
0.025%
IOUTA
OR
IOUTB
tPD
tST
0.025%
0.025%
Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled
–4–
REV. A
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