AD7667 View Datasheet(PDF) - Analog Devices
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AD7667 Datasheet PDF : 28 Pages
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AD7667
SLAVE SERIAL INTERFACE
External Clock
The AD7667 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. Figure 41 and Figure 42 show the detailed timing
diagrams of these methods. Usually, because the AD7667 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.
While the AD7667 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7667 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during
the latter half of BUSY HIGH.
EXT/INT = 1
INVSCLK = 0
RD = 0
RD
BUSY
SCLK
SDOUT
SDIN
t35
t36 t37
1
2
3
t31
t32
X
D15
D14
D13
t16
t34
14
15
16
17
18
D1
D0
X15
X14
X15
X14
X13
t33
X1
X0
Y15
Y14
Figure 41. Slave Serial Data Timing for Reading (Read after Convert)
EXT/INT = 1
INVSCLK = 0
RD = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
SDOUT
1
t31
2
3
t32
X
D15
D14
D13
t16
14
15
16
D1
D0
Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
Rev. 0 | Page 24 of 28
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