TC74
Timing Diagrams
SMBUS READ Timing Diagram
A
B
ILOW
IHIGH
C
D
EF
G
SCL
SDA
H
I
J
K
tSU(START) tH(START)
A = START Condition
B = MSB of Address Clocked into Slave
C = LSB of Address Clocked into Slave
D = R/W Bit Clocked into Slave
tSU-Data
E = Slave Pulls SDA Line Low
F = Acknowledge Bit Clocked into Master
G = MSB of Data Clocked into Master
H = LSB of Data Clocked into Master
I = Acknowledge Clock Pulse
J = STOP Condition
K = New START Condition
tSU(STOP)
tIDLE
SMBUS Write Timing Diagram
A
B
C
D
EF
G
ILOW IHIGH
SCL
SDA
H
IJ
K
L
M
tSU(START) tH(START)
tSU-DATA
tH-DATA
A = START Condition
B = MSB of Address Clocked into Slave
C = LSB of Address Clocked into Slave
D = R/W Bit Clocked into Slave
E = Slave Pulls SDA Line Low
F = Acknowledge Bit Clocked into Master
G = MSB of Data Clocked into Slave
H = LSB of Data Clocked into Slave
I = Slave Pulls SDA Line Low
J = Acknowledge Clocked into Master
K = Acknowledge Clock Pulse
L = STOP Condition, Data Executed by Slave
M = New START Condition
tSU(STOP) tIDLE
DS21462B-page 6
© 2002 Microchip Technology Inc.