MC44251FU View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC44251FU Datasheet PDF : 18 Pages
| |||
DATA OUTPUTS
Symbol
Characteristic
td
Delay from Sample Clock to Valid Output, Figure 2
IOL
IOH
tQLH, tQHL
Output Sinking Current at Vout = 0.4 V
Output Sourcing Current at Vout = VDD – 0.1 V
Propagation Delay from the Clock Rising Edge to Valid Data Output
(CL = 15 pF), Figure 1
IOTR
Maximum Three–State Leakage Current
NOTES:
1. Unit “LSB” means ideal LSB (see definitions section).
2. “Difference” means difference between any two converters in the same package.
CLK
DATA
OUTPUT
tr
tf
90%
50%
10%
twH
twL
tQLH, tQHL
50%
Figure 1. Clock and Output Timing
Min
Max
2.5
2.5
2.0
—
– 0.4
—
—
40
—
± 50
VDD(D)
VSS(D)
Unit
Cycle
mA
mA
ns
µA
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
B7
G0
G1
G2
G3
CS
G4
G5
G6
G7
R0
VDD(D)
R1
R2
R3
VSS(D)
CLK
R4
R5
R6
R7
VSS(A)
Function
Output Blue, Bit 7 (MSB)
Output Green, Bit 0 (LSB)
Output Green, Bit 1
Output Green, Bit 2
Output Green, Bit 3
Chip Select
Output Green, Bit 4
Output Green, Bit 5
Output Green, Bit 6
Output Green, Bit 7 (MSB)
Output Red, Bit 0 (LSB)
VDD, Digital
Output Red, Bit 1
Output Red, Bit 2
Output Red, Bit 3
VSS, Digital
Clock Input
Output Red, Bit 4
Output Red, Bit 5
Output Red, Bit 6
Output Red, Bit 7 (MSB)
VSS, Analog
PIN DESCRIPTIONS
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
HZ
VTN
VDD(R)
RTOP
Rin
RMID
Gin
RBOT
Bin
VSS(R)
IBIAS
VDD(A)
MODE
B0
B1
B2
B3
VSS(D)
B4
B5
B6
VDD(D)
Function
Horizontal Sync
Vertical Sync
VDD, reference
Reference Tapping, Top
Analog Input, Red
Reference Tapping, Middle
Analog Input, Green
Reference Tapping, Bottom
Analog Input, Blue
VSS for Reference Voltage
To External Bias Resistor
VDD, Analog
Clamp Level Select Input
Output Blue, Bit 0 (LSB)
Output Blue, Bit 1
Output Blue, Bit 2
Output Blue, Bit 3
VSS, Digital
Output Blue, Bit 4
Output Blue, Bit 5
Output Blue, Bit 6
VDD, Digital
MC44251
4
MOTOROLA
Share Link: 