AD9608 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9608

10-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

Analog Devices 

AD9608

Pin No.

Mnemonic

Digital Outputs

18

D0+ (LSB)

17

D0− (LSB)

21

D1+

20

D1−

23

D2+

22

D2−

27

D3+

26

D3−

30

D4+

29

D4−

32

D5+

31

D5−

34

D6+

33

D6−

36

D7+

35

D7−

39

D8+

38

D8−

41

D9+ (MSB)

40

D9− (MSB)

43

OR+

42

OR−

25

DCO+

24

DCO−

SPI Control

45

SCLK/DFS

44

SDIO/DCS

46

CSB

ADC Configuration

47

OEB

48

PDWN

Type

Description

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Channel A/Channel B LVDS Output Data 0—True.

Channel A/Channel B LVDS Output Data 0—Complement.

Channel A/Channel B LVDS Output Data 1—True.

Channel A/Channel B LVDS Output Data 1—Complement.

Channel A/Channel B LVDS Output Data 2 —True.

Channel A/Channel B LVDS Output Data 2—Complement.

Channel A/Channel B LVDS Output Data 3—True.

Channel A/Channel B LVDS Output Data 3—Complement.

Channel A/Channel B LVDS Output Data 4—True.

Channel A/Channel B LVDS Output Data 4—Complement.

Channel A/Channel B LVDS Output Data 5—True.

Channel A/Channel B LVDS Output Data 5—Complement.

Channel A/Channel B LVDS Output Data 6—True.

Channel A/Channel B LVDS Output Data 6—Complement.

Channel A/Channel B LVDS Output Data 7—True.

Channel A/Channel B LVDS Output Data 7—Complement.

Channel A/Channel B LVDS Output Data 8—True.

Channel A/Channel B LVDS Output Data 8—Complement.

Channel A/Channel B LVDS Output Data 9—True.

Channel A/Channel B LVDS Output Data 9—Complement.

Channel A/Channel B LVDS Overrange Output—True.

Channel A/Channel B LVDS Overrange Output—Complement.

Channel A/Channel B LVDS Data Clock Output—True.

Channel A/Channel B LVDS Data Clock Output—Complement.

Input

Input/Output

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode.

SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.

SPI Chip Select (Active Low).

Input

Input

Output Enable Input (Active Low). Pin must be enabled via SPI.

Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as

power-down or standby.

Rev. 0 | Page 14 of 40

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