AD7683 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7683 Datasheet PDF : 17 Pages
| |||
Data Sheet
AD7683
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
Throughput Rate
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid
CS Rising Edge to DOUT High Impedance
DCLOCK Falling to Data Valid
Acquisition Time
DOUT Fall Time
DOUT Rise Time
Symbol
tCYC
tCSD
tSUCS
tHDO
tDIS
tEN
tACQ
tF
tR
Min
Typ
Max
Unit
100
kHz
0
μs
20
ns
5
16
ns
14
100
ns
16
50
ns
400
ns
11
25
ns
11
25
ns
Timing and Circuit Diagrams
CS
tSUCS
tCYC
COMPLETE CYCLE
POWER DOWN
DCLOCK
1
45
tCSD
tEN
tHDO
DOUT
HIGH-Z
0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
(MSB)
(LSB)
NOTES
1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
Figure 2. Serial Interface Timing
tACQ
tDIS
HIGH-Z
500µA IOL
TO DOUT
CL
100pF
1.4V
500µA IOH
Figure 3. Load Circuit for Digital Interface Timing
0.8V
tEN
2V
0.8V
2V
tEN
2V
0.8V
Figure 4. Voltage Reference Levels for Timing
DOUT
tR
90%
10%
tF
Figure 5. DOUT Rise and Fall Timing
Rev. B | Page 5 of 16
Share Link: 