ACC2087 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

ACC2087

ENHANCED SUPER CHIP

Unspecified 

ACC MicroTM

2087

Posted Write and Write Through

The ACC2087 cache controller supports write-through and post write cache update options to prevent old data

from being used.

The write-through option is the simplest way to keep cache coherent. In a cache write hit cycle, the memory

controller will update the DRAM at the same time that it is written to the cache. The ACC2087 cache controller

default mode is write-through mode.

Write Back Cache Circuit Block Diagram

The ACC2087 also supports posted write cache system by programming Configuration Register 4h, bit 7=1.

The posted write option allows the data to be buffered before updating to the main memory. The system

performance is therefore increased, since the processor can start a new cycle before the write cycle to the main

memory is completed.

Cache Burst and Line Size

The ACC2087 supports a flexible line size structure and cache burst. The ACC2087 supports 32 bit, 64 bit, or

128 bit line sizes. Configuration Register 4h, bits 2 and 1 determine the line size. In the case of a cache read

hit cycle, the ACC2087 will pull the burst ready signal, BRDY#, low and fill the 486 internal cache lines

quickly. A 128 bit line size requires only 5 cycles to fill the cache lines. A 64 bit line size requires 3 cycles.

In the case of a read miss cycle, the ACC2087 burst mode will generate four continuous DRAM read cycles for

a 128 bit line size to fill both 486 internal and external cache. For a 64 bit line size, the ACC2087 burst mode

will generate two burst cycles instead of four.

2.12 Memory Controller

The Memory Controller is a key feature of the ACC2087. This versatile circuit provides complete control of up

to 64 megabytes of system DRAM. In any control mode, it generates up to four Row Address Strobes

(RAS#0-3) and one Memory Write Enable signal (WEN#). The Memory Controller also provides the interface

to transfer control to a DMA controller or an AT Bus master.

The ACC2087 Memory Controller supports 256KB, 512KB, 1MB and 4MB DRAM devices. The ACC2087

provides all control signals and programmable control to support 256Kx1, 512Kx1, 1Mx1, 1Mx4, 4Mx1 and

4Mx4 (symmetrical only).

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