AD9601BCPZ-250 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9601BCPZ-250 Datasheet PDF : 32 Pages
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AD9601
Addr
(Hex)
09
Parameter Name
clock
Bit 7
(MSB)
0
Bit 6
0
OD test_io
OF ain_config
0
0
14
output_mode
0
0
16
output_phase
Output 0
clock
polarity
1=
inverted
0=
normal
(default)
17
flex_output_delay Output
delay
enable:
0=
enable
1=
disable
18
flex_vref
Bit 5
0
Reset
PN23 gen:
1 = on
0 = off
(default)
0
Interleave
output
mode:
1=
enabled
0=
disabled
(default)
0
Bit 4
0
Reset
PN9 gen:
1 = on
0 = off
(default)
0
Output
enable:
0=
enable
(default)
1=
disable
0
Bit 3 Bit 2
Bit 1
Bit 0
(LSB)
0
0
0
Duty cycle
stabilizer:
0=
disabled
1=
enabled
(default)
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = unused
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by output_mode)
0
Analog CML
0
input
enable:
disable: 1 = on
1 = on
0 = off
0 = off
(default)
(default)
0
Output
Data format select:
invert:
00 = offset binary
1 = on
(default)
0 = off
01 = twos
(default)
complement
10 = Gray code
Default
Value
(Hex)
0x01
0x00
0x00
0x00
0x03
Default Notes/
Comments
When set, the
test data is
placed on the
output pins in
place of normal
data.
Output clock delay:
00000 = 0.1 ns
00001 = 0.2 ns
00010 = 0.3 ns
…
11101 = 3.0 ns
11110 = 3.1 ns
11111 = 3.2 ns
Input voltage range setting:
10000 = 0.98 V
10001 =1.00 V
10010 = 1.02 V
10011 =1.04 V
…
11111 = 1.23 V
00000 = 1.25 V
00001 = 1.27 V
…
01110 = 1.48 V
01111 = 1.50 V
0x00
0x00
Rev. 0 | Page 24 of 32
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