ADIS16209CCCZ(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADIS16209CCCZ
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
ADIS16209CCCZ Datasheet PDF : 16 Pages
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ADIS16209
OUTPUT DATA REGISTERS
Table 7 provides the data configuration for each output data
register in the ADIS16209. Starting with the MSB of the upper
byte, each output data register has the following bit sequence:
new data (ND) flag, error/alarm (EA) flag, followed by 14 data
bits. The data bits are LSB-justified and, in the case of the 12-bit
data formats, the remaining two bits are not used. The ND flag
indicates that unread data resides in the output data registers.
This flag clears and returns to 0 during an output register read
sequence. It returns to 1 after the next internal sample update
cycle completes. The EA flag indicates an error condition. The
STATUS register contains all of the error flags and provides the
ability to investigate root cause.
Table 7. Output Data Register Formats
Register
Bits Format
SUPPLY_OUT 14 Binary, 3.3 V = 0x2A3D
XACCL_OUT 14 Twos complement
YACCL_OUT 14 Twos complement
AUX_ADC
12 Binary, 2 V = 0x0CCC
TEMP_OUT 12 Binary, 25°C = 0x04FE
XINCL_OUT2 14 Twos complement
YINCL_OUT2 14 Twos complement
ROT_OUT3
14 Twos complement
Scale1
0.30518 mV
0.24414 mg
0.24414 mg
0.6105 mV
−0.47°C
0.025°
0.025°
0.025°
1 Scale denotes quantity per LSB.
2 Range is −90° to +90°.
3 Range is −180° to +179.975°.
OPERATION CONTROL REGISTERS
Internal Sample Rate
The SMPL_PRD register controls the ADIS16209 internal sample
rate and has two parts: a selectable time base and a multiplier. The
following relationship produces the sample rate:
tS = tB × NS + 122.07μs
Table 8. SMPL_PRD Bit Descriptions
Bit Description
15:8 Not used
7 Time base (tB)
0 = 244.14 μs, 1 = 7.568 ms
6:0 Increment setting (NS)
(Default = 0x0004)
An example calculation of the default sample period follows:
SMPL_PRD = 0x01, B7 − B0 = 00000001
B7 = 0 → tB = 244.14 μs, B6…B0 = 000000001 → NS = 1
tS = tB × NS + 122.07μs = 244.14 × 1 + 122.07 = 366.21 μs
fS = 1∕tS = 2731 SPS
The sample rate setting has a direct impact on the SPI data
rate capability. For sample rates ≥546 SPS, the SPI SCLK can
run at a rate up to 2.5 MHz. For sample rates <546 SPS, the SPI
SCLK can run at a rate up to 1 MHz. The sample rate setting
also affects power dissipation. When the sample rate is set to
<546 SPS, power dissipation typically reduces by a factor
of 68%. The two different modes of operation offer a system-
level trade-off between performance (sample rate, serial transfer
rate) and power dissipation.
Power Management
In addition to offering two different performance modes for
power optimization, the ADIS16209 offers a programmable
shutdown period that the SLP_CNT register controls.
Table 9. SLP_CNT Bit Descriptions
Bit
Description
15:8 Not used
7:0
Data bits, 0.5 seconds/LSB
(Default = 0x0000)
For example, writing 0x08 to the SLP_CNT register places the
ADIS16209 into sleep mode for 4 seconds. The only way to stop
this process is to remove power or reset the device.
Digital Filtering
The AVG_CNT register controls the moving average digital filter,
which determines the size of the moving average filter, in eight
power-of-two step sizes (that is, 2M = 1, 2, 4, 16, 32, 64, 128, and
256). Filter setup requires one simple step: write the appropriate
M factor to the assigned bits in the AVG_CNT register.
Table 10. AVG_CNT Bit Descriptions
Bit Description
(Default = 0x0004)
15:4 Not used
3:0 Power-of-two step size, maximum binary value = 1000
The following equation offers a frequency response relationship
for this filter:
H
A(
f
)
=
sin(π× N ×
N × sin(π ×
f
f
×tS
×tS
)
)
20
N=4
0
N = 128
N = 16
–20
–40
–60
–80
–100
0.001
0.01
0.1
f/fS
Figure 21. Frequency Response—Moving Average Filter
Rev. 0 | Page 12 of 16
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