EP1C12T173C6 View Datasheet(PDF) - Altera Corporation

Part Name

Description

Manufacturer

EP1C12T173C6

Cyclone FPGA Family

Altera Corporation 

Timing Model

Table 4–51. Cyclone Maximum Output Clock Rate for Row Pins

I/O Standard

LVTTL

2.5 V

1.8 V

1.5 V

LVCMOS

SSTL-3 class I

SSTL-3 class II

SSTL-2 class I

SSTL-2 class II

3.3-V PCI (1)

LVDS

-6 Speed

Grade

296

381

286

219

367

169

160

160

131

66

320

-7 Speed

Grade

285

366

277

208

356

166

151

151

123

66

303

-8 Speed

Grade

273

349

267

195

343

162

146

142

115

66

275

Unit

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

Note to Tables 4–50 through 4–51:

(1) EP1C3 devices do not support the PCI I/O standard. These parameters are only

available on row I/O pins.

PLL Timing

Table 4–52 describes the Cyclone FPGA PLL specifications.

Table 4–52. Cyclone PLL Specifications (Part 1 of 2)

Symbol

fIN

fIN DUTY

tIN JITTER

fOUT_EXT (external PLL

clock output)

Parameter

Input frequency (-6 speed

grade)

Input frequency (-7 speed

grade)

Input frequency (-8 speed

grade)

Input clock duty cycle

Input clock period jitter

PLL output frequency

(-6 speed grade)

PLL output frequency

(-7 speed grade)

PLL output frequency

(-8 speed grade)

Min

15.625

15.625

15.625

40.00

15.625

15.625

15.625

Max

464

428

387

60

± 200

320

320

275

Unit

MHz

MHz

MHz

%

ps

MHz

MHz

MHz

Altera Corporation

January 2007

4–29

Preliminary

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