ISL12021 View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

ISL12021

Real Time Clock with On Chip Temp Compensation ±5ppm

Intersil 

ISL12021

I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -20°C to +70°C, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

TYP

MIN

(Note 7)

MAX

UNITS NOTES

VIL

SDA and SCL input buffer LOW

voltage

-0.3

0.3 x VDD

V

VIH

SDA and SCL Input Buffer HIGH

Voltage

0.7 x VDD

VDD + 0.3

V

Hysteresis SDA and SCL Input Buffer

Hysteresis

0.05 x VDD

V

VOL

SDA Output Buffer LOW Voltage, VDD = 5V, IOL = 3mA

Sinking 3mA

0.4

V

CPIN

fSCL

tIN

SDA and SCL Pin Capacitance

SCL Frequency

Pulse Width Suppression Time at

SDA and SCL Inputs

TA = +25°C, f = 1MHz,

VDD = 5V, VIN = 0V,

VOUT = 0V

Any pulse narrower than the

max spec is suppressed.

10

pF

400

kHz

50

ns

tAA

tBUF

SCL Falling Edge To SDA Output

Data Valid

Time the Bus Must be Free Before

The Start of a New Transmission

SCL falling edge crossing 30%

of VDD, until SDA exits the

30% to 70% of VDD window.

SDA crossing 70% of VDD

during a STOP condition, to

SDA crossing 70% of VDD

during the following START

condition.

1300

900

ns

ns

tLOW Clock LOW Time

Measured at the 30% of VDD

1300

ns

crossing.

tHIGH Clock HIGH Time

Measured at the 70% of VDD

600

ns

crossing.

tSU:STA START Condition Setup Time

tHD:STA START Condition Hold Time

tSU:DAT Input Data Setup Time

tHD:DAT Input Data Hold Time

tSU:STO STOP Condition Setup Time

tHD:STO STOP Condition Hold Time

tDH

Output Data Hold Time

SCL rising edge to SDA falling

600

edge. Both crossing 70% of

VDD.

From SDA falling edge

600

crossing 30% of VDD to SCL

falling edge crossing 70% of

VDD.

From SDA exiting the 30% to

100

70% of VDD window, to SCL

rising edge crossing 30% of

VDD.

From SCL falling edge

0

crossing 30% of VDD to SDA

entering the 30% to 70% of

VDD window.

From SCL rising edge

600

crossing 70% of VDD, to SDA

rising edge crossing 30% of

VDD.

From SDA rising edge to SCL

600

falling edge. Both crossing

70% of VDD.

From SCL falling edge

0

crossing 30% of VDD, until

SDA enters the 30% to 70% of

VDD window.

ns

ns

ns

900

ns

ns

ns

ns

4

FN6451.0

March 30, 2007

Share Link: