IS42S16400L View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

IS42S16400L

2(1)M Words x 8(16) Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Unspecified 

IS42S8800/IS42S8800L

IS42S16400/IS42S16400L

2(1)M Words x 8(16) Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

FEATURES

• Single 3.3V (± 0.3V) power supply

• High speed clock cycle time -7: 133MHz<3-3-3>,

-8: 100MHz<2-2-2>

• Fully synchronous operation referenced to clock

rising edge

• Possible to assert random column access in

every cycle

• Quad internal banks contorlled by A12 & A13

(Bank Select)

• Byte control by LDQM and UDQM for

IS42S16400

• Programmable Wrap sequence (Sequential /

Interleave)

• Programmable burst length (1, 2, 4, 8 and full

page)

• Programmable /CAS latency (2 and 3)

• Automatic precharge and controlled precharge

• CBR (Auto) refresh and self refresh

• X8, X16 organization

• LVTTL compatible inputs and outputs

• 4,096 refresh cycles / 64ms

• Burst termination by Burst stop and Precharge

command

• Package 400mil 54-pin TSOP-2

DESCRIPTION

The IS42S8800 and IS42S16400 are high-speed 67,

108,864-bit synchronous dynamic random-access

moeories, organized as 2,097,152 x 8 x 4 and 1,048,

576 x 16 x 4 (word x bit x bank), respectively.

The synchronous DRAMs achieved high-speed data

transfer using the pipeline architecture and clock

frequency up to 133MHz for -7. All input and outputs

are synchronized with the postive edge of the clock.

The synchronous DRAMs are compatible with Low

Voltage TTL (LVTTL).These products are pack-aged

in 54-pin TSOP-2.

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

Integrated Circuit Solution Inc.

1

DR007-0A

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