深圳市天微电子有限公司
SHENZHEN TI TAN M I CRO ELECTRONI CS CO. , LTD.
PIN CONFIGURATION
NC
DIO
SCLK
STB
K1
K2
VDD
SG1/KS1
SG2/KS2
SG3/KS3
SG4/KS4
SG5/KS5
SG6/KS6
SG7/KS7
1
28
2 TM1628 27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
GND
GRID1
GRID2
GND
GRID3
GRID4
GND
VDD
SEG14/GRID5
SEG13/GRID6
SEG12/GRID7
SEG10
SEG9
SEG8/KS8
PIN DESCRIPTION
Pin Name I/O
Description
DIO
I/O
Data Input Output Pin
( N-Channel , Open-Drain) This pin
outputs serial data at the falling edge of
the shift clock. This pin inputs serial data
at the rising edge of the shift clock
(starting from the lower bit)
SCLK
I
Clock Input Pin
This pin reads serial data at the rising
edge and outputs data at the falling edge.
STB
I
Serial Interface Strobe Pin
The data input after the STB has fallen is
processed as a command. When t his pin
is "HIGH", CLK is ignored.
K1,K2
I
Key Data Input Pins
The data sent to these pins are latched at
the end of the display cycle.(Internal
Pull-Low Resistor)
GND
-
Ground Pin
SEG1-SEG8
O Segment Output Pins (p - channel, open
drain) Also acts as the Key Source
SEG9-SEG10
O Segment Output pins (P-Channel, open
drain)
SG12-SEG14 O
Segment/Grid Output Pins
VDD
-
Power Supply
GRID1-GRID4 O
Grid Output Pins
1
No Connection
Pin No.
2
3
4
5,6
22,25,28
8-15
16,17
18-20
21
23,24,26,27
1
Add:522,5/F,Bldg. No.4,Keji Central Road 2, Software Park,High-Tech Industrial Park,Shenzhen
Tel:86-755-86185092
Fax: 86-755-86185093
Web: www.titanmec.com
2