AGL060V5-QNG144 View Datasheet(PDF) - Microsemi Corporation
Part Name
Description
Manufacturer
AGL060V5-QNG144 Datasheet PDF : 250 Pages
| |||
Revision
Revision 19
(continued)
IGLOO Low Power Flash FPGAs
Changes
Page
Values for CS196, CS281, and QN132 packages were added to Table 2-5 • Package 2-6
Thermal Resistivities (SARs 26228, 32301).
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to 2-7
TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and Voltage Derating Factors
for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) were updated to remove
the column for –20°C and shift the data over to correct columns (SAR 23041).
The tables in the "Quiescent Supply Current" section were updated with revised notes 2-7
on IDD (SAR 24112). Table 2-8 • Power Supply State per Mode is new.
The formulas in the table notes for Table 2-41 • I/O Weak Pull-Up/Pull-Down 2-37
Resistances were corrected (SAR 21348).
The row for 110°C was removed from Table 2-45 • Duration of Short Circuit Event
before Failure. The example in the associated paragraph was changed from 110°C to
100°C. Table 2-46 • I/O Input Rise Time, Fall Time, and Related I/O Reliability1 was
revised to change 110° to 100°C. (SAR 26259).
2-40
The notes regarding drive strength in the "Summary of I/O Timing Characteristics –
Default I/O Software Settings" section, "3.3 V LVCMOS Wide Range" section and "1.2
V LVCMOS Wide Range" section tables were revised for clarification. They now state
that the minimum drive strength for the default software configuration when run in wide
range is ±100 µA. The drive strength displayed in software is supported in normal range
only. For a detailed I/V curve, refer to the IBIS models (SAR 25700).
2-28,
2-47,
2-76
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 24916): "It 2-56
uses a 5 V–tolerant input buffer and push-pull output buffer."
The values for FDDRIMAX and FDDOMAX were updated in the tables in the "Input DDR 2-92,
Module" section and "Output DDR Module" section (SAR 23919).
2-95
The following notes were removed from Table 2-147 • Minimum and Maximum DC Input 2-80
and Output Levels (SAR 29428):
±5%
Differential input voltage = ±350 mV
Table 2-189 • IGLOO CCC/PLL Specification and Table 2-190 • IGLOO CCC/PLL
Specification were updated. A note was added to both tables indicating that when the
CCC/PLL core is generated by Mircosemi core generator software, not all delay values
of the specified delay increments are available (SAR 25705).
2-113
The following figures were deleted (SAR 29991). Reference was made to a new N/A
application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs, which covers these cases in detail (SAR 21770).
Figure 2-36 • Write Access after Write onto Same Address
Figure 2-37 • Read Access after Write onto Same Address
Figure 2-38 • Write Access after Read onto Same Address
2-117 to
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" 2-128
tables, Figure 2-40 • FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SARs 29991, 30510).
The "Pin Descriptions" chapter has been added (SAR 21642).
3-1
Package names used in the "Package Pin Assignments" section were revised to match 4-1
standards given in Package Mechanical Drawings (SAR 27395).
The "CS81" pin table for AGL250 is new (SAR 22737).
4-5
The CS121 pin table for AGL125 is new (SAR 22737).
The P3 function was revised in the "CS196" pin table for AGL250 (SAR 24800).
4-12
Revision 23
5-3
Share Link: 