NHI-15191RT View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

NHI-15191RT

Multi-Protocol Data Bus Interface NHi-RT Expanded Memory Remote Terminals

Unspecified 

PRESET

Bits: (4: 0)

These bits provide a method to perform a double word( 32 bit) preset to the RTC. When this bit

field is set to any number from 1 to 30( bit 0 = LSB), the first two words of a receive message

whose subaddress is equal to this value will be used to preset the internal RTC. The most

significant word is received first. If this field is equal to a "0" or "31", the RTC will not be preset.

All bits in this register are cleared during initialization of the RT.

4.2.10 FIFO READ

Address: 8 R

This address is used to read the contents of the interrupt FIFO. Reading this address pops the

FIFO, updates the IVR and the AVR; then outputs the AVR(upper byte) and IVR(lower byte).

4.2.11 FIFO RESET

Address: 8 W

Writing any value to this address empties the FIFO.

4.2.12 LAST COMMAND REGISTER Address: 11 R

This register holds the last command word as defined by MIL-Bus. The contents are not defined

after initialization of the RT.

4.2.13 LAST STATUS REGISTER

Address: 12 R

This register holds the last status word as defined by MIL- STD- 1553B. After initialization of the

BUSY bit= 1, the TADR field contains the hardwire address, and all other bits are set to 0. See

RTC CONTROL REGISTER for special options.

4.2.14 RESET REMOTE TERMINAL Address: 15 W

Writing a word to address 15 resets the RT and causes it to perform its initialization (see

initialization section).

4.2.15 ENCODER STATUS

Address: 18

R

This register contains flags indicating the status of the encoder. These flags are intended to

facilitate transmission of messages in loop- back mode during self- test.

15

TXREQ_L

7

EOTX_L

0

FAILSAFE_L

TXREQ_ L

Bits: 15

0= Indicates that the encoder is ready to accept the next word for transmission. This bit should

equal "0" before loading the Encoder Data register with the next word. In order to transmit

contiguous words, the next word should be loaded within 18 microseconds after *TXREQ

transitions to "0".

EOTX_ L

Bits: 7

0= Indicates that the encoder has completed transmission and that there are no pending

requests.

FAILSAFE_ L

Bits: 0

0= FAILSAFE TIME OUT has occurred. This bit will be set to a "1" when a new message is

received or during a reset.

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