QS5LV919 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

QS5LV919

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

Integrated Device Technology 

QS5LV919

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

AC TIMING DIAGRAM

SYNC

FEEDBACK

Q

Q0-Q4

Q /2

2xQ

Q5

tS K F

tSKALL

INDUSTRIAL TEMPERATURE RANGE

tP D

tJ

tS K R

NOTES:

1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the negative edge of SYNC

input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC.

2. All parameters are measured at 0.5VDD.

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