Table 18 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V)
Symbol
Parameter
Min Typ Max Unit
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time (RAM)
Access Time (command)
100 500
-
ns
0
-
25
ns
0
-
-
ns
30
-
-
ns
5
-
-
ns
10
-
50
ns
-
-
40
ns
15
-
15
-
-
ns
-
ns
PWCSL Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
250 -
250 -
-
ns
-
ns
Chip Select Low Pulse Width (write)
50
-
-
ns
PWCSH Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
100 -
50
-
-
ns
-
ns
tR
Rise Time
tF
Fall Time
-
-
10
ns
-
-
10
ns
D/C
tAS
tAH
WR (R/W)
RD (E)
CS
D0-D7
(Write dat a to driver)
(Read daDta0-frDo7m driver)
P WC SL
tcycl e
PW C SH
tF
tR
tD SW
tDHW
Valid Data
tAC C
Valid Data
tDHR
tOH
Figure 17 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)
41
SSD1858
Rev 1.1
09/2002
SOLOMON