IDT72V36110L6BBGI View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT72V36110L6BBGI

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

Integrated Device Technology 

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

65,536 x 36 and 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK

tENS

REN

Q0 - Qn

Wx

WCLK

WEN

RT

1

2

Wx+1

tRTS

tENS

tA

tA

W1

tSKEW2

1

2

tENH

3

tA

W2 (4)

4

tA

W3 (4)

5

tENH

tA

W4 (4)

W5

OR

tPAES

PAE

tHF

HF

tPAFS

PAF

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NOTES:

1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.

2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.

D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.

3. OE = LOW.

4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.

5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.

6. RM is set LOW during MRS.

Figure 14. Zero Latency Retransmit Timing (FWFT Mode)

WCLK

SEN

LD

SI

t ENS

tLDS

tDS

BIT 0

tENH

tLDH

EMPTY OFFSET

NOTE:

1. X = 15 for the IDT72V36100 and X = 16 for the IDT72V36110.

(1)

BIT X

BIT 0

FULL OFFSET

tENH

tLDH

tDH

(1)

BIT X

Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

34

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