IDT72V36110L6BBGI View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT72V36110L6BBGI

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

Integrated Device Technology 

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

65,536 x 36 and 131,072 x 36

tCLKH

tCLKL

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

WEN

tENS

tENH

PAE

RCLK

n words in FIFO(2),

n + 1 words in FIFO(3)

tPAEA

n + 1 words in FIFO(2),

n + 2 words in FIFO(3)

tPAEA

tENS

n words in FIFO(2),

n + 1 words in FIFO(3)

REN

NOTES:

1. n = PAE offset.

2. For IDT Standard Mode.

3. For FWFT Mode.

4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.

5. Select this mode by setting PFM LOW during Master Reset.

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Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

WCLK

WEN

HF

RCLK

REN

tCLKH

tCLKL

tENS

D/2 words in FIFO(1),

[ ] D-1

2

+

1

words in FIFO(2)

tENH

tHF

D/2 + 1 words in FIFO(1),

[ ] D-1

2 +2

words in FIFO(2)

tHF

tENS

NOTES:

1. In IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.

2. In FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.

Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)

37

D/2 words in FIFO(1),

[ ] D-1

2 +1

words in FIFO(2)

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