IDT72V36110L6BBGI View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT72V36110L6BBGI

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

Integrated Device Technology 

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

65,536 x 36 and 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

JTAG INTERFACE

Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to

support the JTAG boundary scan interface. The IDT72V36100/72V36110

incorporates the necessary tap controller and modified pad cells to implement

the JTAG facility.

Note that IDT provides appropriate Boundary Scan Description Language

program files for these devices.

The Standard JTAG interface consists of four basic elements:

• Test Access Port (TAP)

• TAP controller

• Instruction Register (IR)

• Data Register Port (DR)

The following sections provide a brief description of each element. For a

complete description refer to the IEEE Standard Test Access Port Specification

(IEEE Std. 1149.1-1990).

The Figure below shows the standard Boundary-Scan Architecture

TDO

TDI

T

A

TMS P

TCLK

TRST

DeviceID Reg.

Boundary Scan Reg.

Bypass Reg.

Mux

clkDR, ShiftDR

UpdateDR

TAP

Cont-

roller

clklR, ShiftlR

UpdatelR

Instruction Decode

Instruction Register

Control Signals

Figure 32. Boundary Scan Architecture

6117 drw37

TEST ACCESS PORT (TAP)

The Tap interface is a general-purpose port that provides access to the

internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)

and one output port (TDO).

THE TAP CONTROLLER

The Tap controller is a synchronous finite state machine that responds to

TMS and TCLK signals to generate clock and control signals to the Instruction

and Data Registers for capture and update of data.

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