MAX1816ETM View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX1816ETM

Dual Step-Down Controllers Plus Linear-Regulator Controller for Notebook Computers

Maxim Integrated 

Dual Step-Down Controllers Plus Linear-

Regulator Controller for Notebook Computers

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,

TA = -40°C to +100°C, unless otherwise noted.) (Note 6)

PARAMETER

CONDITIONS

MIN TYP MAX UNITS

SKP1/SDN, SKP2/SDN Skip

Level

SKP1/SDN, SKP2/SDN logic input high level

2.8

V

SKP1/SDN, SKP2/SDN PWM

Level

SKP1/SDN, SKP2/SDN logic input float level

1.4

2.2

V

SKP1/SDN, SKP2/SDN Shutdown

Level

SKP1/SDN, SKP2/SDN logic input low level

0.4

V

PGOOD Lower Trip Threshold

Measured at FBS, OUT2, and FB2 with respect to unloaded

output voltage, falling edge, typical hysteresis = 1%

-12.5

-7.5

%

LINGOOD Lower Trip Threshold

and LINFB Undervoltage

Protection Threshold

Measured at LINFB with respect to unloaded output

voltage, falling edge (Note 5)

-12.5

-7.5

%

PGOOD Upper Trip Threshold

Measured at FBS, OUT_, FB2 with respect to unloaded

7.5

output voltage, rising edge, typical hysteresis = 1%

12.5

%

LINGOOD Upper Trip Threshold

and LINFB Overvoltage Trip

Measured at LINFB with respect to unloaded output

7.5

Threshold

voltage, rising edge (Note 5)

12.5

%

LINGOOD Turn-On Delay

LINFB forced 2% above LINGOOD lower trip threshold

1

Open-Drain Output Low Voltage

(PGOOD, LINGOOD)

ISINK = 3mA

ms

0.4

V

OFS Positive Offset when

Programmed to Zero

OFS Gain

Deviation in the output voltage when tested with OFS_

connected to REF

∆VOUT / ∆VOFS, ∆VOFS = (0.8V - 0V)

∆VOUT / ∆VOFS, ∆VOFS = (2.0V - 1.2V)

0.119

0.119

2

mV

0.131

V/V

0.131

Note 1: DC output accuracy specifications for BUCK2 refer to the trip level of the error amp. The output voltage has a DC regulation

higher than the trip level by 50% of the ripple. In SKIP mode, the output rises by approximately 1.5% when transitioning from

continuous conduction to no load.

Note 2: On-time and minimum off-time specifications for both BUCK1 and BUCK2 are measured from 50% to 50% at the DH_ pin

with LX_ forced to zero, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate

capacitance. Actual in-circuit times can be different due to MOSFET switching speeds.

Note 3: This does not include the time for REF to start up if required.

Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin

QFN package.

Note 5: The LINGOOD signal is latched low under a fault condition of LINFB dropping below 90% or rising above 110% of the nomi-

nal set point. The LINGOOD signal does not go high again until the fault latch is reset.

Note 6: Specifications from -40°C to +100°C are guaranteed by design, not production tested.

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