2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
OUTPUT2
12V/0.2A
OUTPUT2
PGND
SGND
PGOOD2
PGOOD1
VL
CLOCK
OUT
ON
OFF
28 27 26 25 24 23 22
SOURCE2 PGND SGND SOURCE1 PGOOD2
1 CLKOUT
2 BST2/VDD2 EP
PGOOD1 21
SGND
BST1/VDD1 20
3 DRAIN2
DRAIN1 19
4 DRAIN2
5 EN2
MAX5073
DRAIN1 18
EN1 17
6 FB2
FB1 16
7 COMP2
COMP1 15
SYNC N.C. OSC V+ VL VL BYPASS
8 9 10 11 12 13 14
OUTPUT1
VL
ON
OFF
INPUT
OUTPUT1
3.3V/2A
SYSTEM
CLOCK
INPUT
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR
THE RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
Figure 8. Buck-Boost Application
Boost Converter Compensation
The boost converter compensation gets complicated
due to the presence of a right-half-plane zero fZERO,RHP.
The right-half-plane zero causes a drop in-phase while
adding positive (+1) slope to the gain curve. It is impor-
tant to drop the gain significantly below unity before the
RHP frequency. Use the following procedure to calcu-
late the compensation components.
1) Calculate the LC double-pole frequency, FLC, and
the right half plane zero frequency.
fLC =
1− D
2π × LOUTCOUT
fZERO, RHP
=
(1 − D)2 R(MIN)
2π × LOUT
where:
D = 1 − VIN
VOUT
R(MIN) = VOUT
IOUT(MAX)
Target the unity-gain crossover frequency for:
fC ≤ fZERO, RHP
5
2) Place a zero
(fZ1
=
2π
1
× RF
×
)
CF
at 0.75 x fLC.
CF
=
2π
×
1
0.75 ×
fLC
×
RF
where RF ≥ 10kΩ.
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