MAX9526AEI/V-T(2010) View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX9526AEI/V-T
(Rev.:2010)

Low-Power, High-Performance NTSC/PAL Video Decoder

Maxim Integrated 

Low-Power, High-Performance

NTSC/PAL Video Decoder

Clock and Output Control Register

REG

B7

B6

B5

0x0D

0

CLIP

LLC_INV

B4

SEL_54MHZ

B3

XTAL_DIS

B2

HSVS

B1

DATAZ

B0

LLCZ

ITU-R BT.656 Standard Clipping Level (CLIP)

1 = Clip ITU output to Y range is between 64–940 and

CbCr range is between 64–960.

0 = Clip ITU output to Y range and CbCr range is

between 5–1019 (default).

Inverted Line-Locked Clock (LLC_INV)

This signal inverts the polarity of the line-locked clock

that is output from the MAX9526. This can be used to

solve board level timing problems for other devices.

1 = Invert LLC clock.

0 = Do not invert LLC clock (default).

Input Clock Frequency Select (SEL_54MHz)

1 = 54MHz clock at XTAL/OSC input.

0 = 27MHz clock at XTAL/OSC input (default).

This bit is only applicable when the crystal oscillator is

disabled (XTAL_DIS = 1).

Crystal Oscillator Disable (XTAL_DIS)

1 = XTAL/OSC is either a 27MHz or a 54MHz CMOS

clock input.

0 = Enables the 27MHz crystal oscillator (default).

Horizontal/Vertical Sync Output (HSVS)

1 = D1 and D0 output horizontal and vertical sync

pulses, respectively.

0 = D1 and D0 are LSBs of digital component video

output (default).

The rising edge of horizontal sync (HS) coincides with

the end of active video (rises after 3FFh 000h of EAV

code). The falling edge coincides with the start of

active video (SAV) code (falls after completing 3FFh

000h of SAV code). Figure 17 shows the horizontal and

vertical sync timing.

The vertical sync pulse (VS) line transitions are detailed

in Table 8. Note that the VS line transitions on pin D0

are shifted by 1 to 2 lines relative to the V flag transi-

tions embedded in the ITU data stream. The V flag tran-

sitions embedded in the ITU data stream follow the

ITU-R BT.656-4 standard.

Data Output Disable (DATAZ)

1 = Logic data outputs (D9–D0) are disabled and

placed in high-impedance state.

0 = Logic data outputs (D9–D0) are enabled (default).

The DATAZ bit forces data outputs high impedance

regardless of whether the device is in shutdown.

Clock Output Disable (LLCZ)

1 = Logic clock output (LLC) are disabled and placed

in a high-impedance state.

0 = Logic clock output (LLC) is enabled (default).

The LLCZ bit forces LLC high impedance regardless of

whether the device is in shutdown.

Table 8. VS (Pin D0) Line Transitions

VERTICAL SYNC PULSES

(VS on Pin D0)

Field 1

Start (VS = 1)

Finish (VS = 0)

Field 2

Start (VS = 1)

Finish (VS = 0)

625

Line 623

Line 21

Line 309

Line 335

525

Line 2

Line 21

Line 265

Line 284

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