MT48LC16M16A2BB-6A(2007) View Datasheet(PDF) - Micron Technology
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MT48LC16M16A2BB-6A Datasheet PDF : 77 Pages
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256Mb: x4, x8, x16 SDRAM
Electrical Specifications
Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6A)
Notes 5, 6, 8, 9, 11, 31 apply to the entire table; notes appear on page 54
-6A
Parameter
Symbol
Min
Max
Units
Notes
Access time from CLK (positive edge)
CL = 3
tAC(3)
–
5.4
ns
27
Address hold time
tAH
0.8
–
ns
Address setup time
tAS
1.5
–
ns
CLK high-level width
tCH
2.5
–
ns
CLK low-level width
tCL
2.5
–
ns
Clock cycle time
CL = 3
tCK(3)
6
–
ns
23
CKE hold time
tCKH
0.8
–
ns
CKE setup time
tCKS
1.5
–
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
0.8
–
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
1.5
ns
Data-in hold time
tDH
0.8
–
ns
Data-in setup time
tDS
1.5
–
ns
Data-out high-impedance time
CL = 3
tHZ(3)
–
5.4
ns
10
Data-out low-impedance time
tLZ
1
–
ns
Data-out hold time (load)
tOH
3
–
ns
Data-out hold time (no load)
tOHN
1.8
–
ns
28
ACTIVE to PRECHARGE command
tRAS
42
120,000
ns
ACTIVE to ACTIVE command period
tRC
60
–
ns
ACTIVE to READ or WRITE delay
tRCD
18
–
ns
Refresh period
tREF
–
64
ms
AUTO REFRESH period
tRFC
60
–
ns
PRECHARGE command period
tRP
18
–
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
12
–
ns
7
Transition time
WRITE recovery time1
tT
0.3
1.2
tWR
1 CLK + 6ns
–
12
–
ns
ns
ns
25
Exit SELF REFRESH to ACTIVE command
tXSR
67
–
ns
20
Notes: 1. Auto precharge mode only. The precharge timing budget (tRP) begins 6ns for -6A after the
first clock delay, after the last WRITE is executed. May not exceed limit set for precharge
mode.
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
51
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