MT48LC16M16A2BB-6A(2007) View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC16M16A2BB-6A Datasheet PDF : 77 Pages
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256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 50: Single Write – Without Auto Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP 2
NOP 2
PRECHARGE
NOP
ACTIVE
NOP
DQM/
DQML, DQMU
A0–A9, A11
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m3
DISABLE AUTO PRECHARGE
BANK
ALL BANKS
SINGLE BANK
BANK
ROW
BANK
tDS tDH
DQ
DIN m
tRCD
t WR4
tRP
tRAS
tRC
DON’T CARE
Notes:
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of fre-
quency. With a single WRITE, tWR has been increased to meet minimum tRAS
requirement.
3. x16: A8, A9, and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
4. PRECHARGE command not allowed (would violate tRAS).
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
70
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©1999 Micron Technology, Inc. All rights reserved.
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