Philips Semiconductors
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
Product specification
74LVC16374A/
74LVCH16374A
PIN DESCRIPTION
PIN NUMBER SYMBOL
1
1OE
2, 3, 5, 6, 8, 9,
11, 12
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42
13, 14, 16, 17,
19, 20, 22, 23
1Q0 to 1Q7
GND
VCC
2Q0 to 2Q7
24
2OE
25
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
48
2CP
2D0 to 2D7
1D0 to 1D7
1CP
NAME AND FUNCTION
Output enable input
(active LOW)
3-State flip-flop outputs
Ground (0V)
Positive supply voltage
3-State flip-flop outputs
Output enable input
(active LOW)
Clock input
Data inputs
Data inputs
Clock input
LOGIC SYMBOL
1
24
1OE 2OE
47
1D0
1Q0
2
46
1D1
44
1D2
1Q1
3
1Q2
5
43
1D3
41
1D4
1Q3
6
1Q4
8
40
1D5
38
1D6
1Q5
9
1Q6
11
37
1D7
1Q7
12
36
2D0
2Q0
13
35
2D1
2Q1
14
33
2D2
2Q2
16
32
2D3
2Q3
17
30
2D4
2Q4
19
29
2D5
2Q5
20
27
2D6
2Q6
22
26
2D7
2Q7
23
1CP 2CP
48 25
SW00075
LOGIC DIAGRAM
1D0
DQ
1Q0
2D0
CP
FF1
1CP
1OE
2CP
2OE
TO 7 OTHER CHANNELS
FUNCTION TABLE
OPERATING MODES
nOE
INPUTS
nCP
Load and read register
L
°
L
°
Load register and disable outputs
H
H
°
°
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high impedance OFF-state
° = LOW-to-HIGH CP transition
DQ
2Q0
CP
FF9
TO 7 OTHER CHANNELS
SW00076
INTERNAL
nDx
FLIP-FLOPS
l
L
h
H
l
L
h
H
OUTPUTS
Q0 to Q7
L
H
Z
Z
1998 Mar 17
3