SC2422ACSTR View Datasheet(PDF) - Semtech Corporation
Part Name
Description
Manufacturer
SC2422ACSTR Datasheet PDF : 10 Pages
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BIPHASE CURRENT MODE
CONTROLLER
SC2422A
PRELIMINARY - August 7, 2000
Programming the DAC Step Size
The SC2422A allows programming the output voltage
and the DAC step size by selecting external resistors.
The DAC current step size, for one MSB is:
IDAC _ MSB
=
VBG
R REF
where RREF is the resistor from RREF pin to Ground.
The DAC MSB voltage step size is calculated as fol-
lows:
VDAC_MSB = IDAC_MSB * RI
VDAC _ LSB
=
VDAC _ MSB
32
or
VDAC _ LSB
= VBG
R REF
∗ RI
32
Note that changing RREF affects both frequency and
DAC step size. RI must be proportionally adjusted to
keep the same step size at different frequencies. The
advantage of this method is that all new VID specifica-
tions can be accommodated by modifying external
components while maintaining the required precision
without the need for converter redesign.
Programming the DAC Offset Voltage
Kirchoff’s current law can be applied to the error ampli-
fier’s Inverting node (see figure 2) to calculate ROS, the
DAC offset setting resistor. The output Offset at zero
DAC current (VID=00000), is set as follows:
R OS
=
VBG
VO − VBG + VEO
− VBG
RI
RF
Where VEO is the error amplifier output voltage and as
a first approximation is equal to 1.75V.
Where VBG = Precision Reference Voltage = 1.50V.
The value of ROS can be fine trimmed using a poten-
tiometer connected from the FB pin to ground.
Programming the Dynamic (Active) Droop
The SC2422A employs a novel approach to active
drooping for optimum transient response. The output
voltage is regulated as a function of output current. At
zero current the output is regulated to the upper limit of
© 2000 SEMTECH CORP.
the output voltage specification. As the load is in-
creased, the output “droops” towards the lower limit.
This makes optimum use of the output voltage error
band, yielding minimum output capacitor size and cost.
Active drooping, does not compromise the converter
response time as does passive droop techniques. The
active droop also allows for an accurate Inter-Module
current sharing scheme, where multiple DC/DC con-
verters are required to share the current required by a
DC bus. As one module supplies more current, that
modules output voltage ”droops”, allowing other mod-
ules to provide the balance of the required current.Any
changes in the output voltage is instantaneously re-
flected to the error amplifier, which has a high Slew
Rate and wide Gain-Bandwidth product to recover the
output voltage to its nominal level with minimal delay.
The droop is adjusted by setting the feedback resistor,
Rf. While the optimum value of RF may be derived ex-
perimentally, the following equation can provide the
droop at a given output current:
VDROOP
=
G CA
* RI * RS
2RF
* IOUT
The Gain of the current amplifier is set to 20 (26dB),
while RS is the input sense resistor.
The effective inductance of the sense resistor must be
minimized to achieve accurate correlation between the
above equation and actual droop achieved. This is be-
cause the inductive spike, which may also be caused
by layout inductance's, will alter the PWM comparator
trip point. The value of RF may have to be adjusted to
compensate for such parasitic effects.
Since Rf also sets the DC gain of the system, changing
the value of Rf affects the offset voltage, which is set
via Ros. The value of Ros can be modified to achieve
exact offset after the droop resistor has been chosen.It
must be noted that the Current Amplifier gain is quite
precise, with greater than 80dB of Common Mode Re-
jection Ratio (CMRR). Thus the droop’s accuracy is
limited primarily by external components tolerances
and the external parasitic effects.
Loop Gain Considerations
The Modulator gain in Input Current Mode control is
equal to:
K MOD
=
VIN
VRAMP
VRAMP
= 0.3V + RSENSE
X TOSC
X GCA
X
VIN − VO
L
8
652 MITCHELL ROAD NEWBURY PARK CA 91320
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