UDA1320 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
UDA1320 Datasheet PDF : 20 Pages
| |||
Philips Semiconductors
Low-cost stereo filter DAC
Preliminary specification
UDA1320ATS
Table 5 Data transfer of type ‘status’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REGISTER SELECTED
0
0 SC1 SC0 IF2 IF1 IF0 0 System Clock frequency (1 : 0);
data Input Format (2 : 0)
1
0
0
0
0
0
0
0 reserved
Table 6 Data transfer of type ‘data’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REGISTER SELECTED
0
0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0)
0
1
0
0
0
0
0
0 reserved
1
0
0 DE1 DE0 MT 0
0 DE-emphasis (1 : 0); MuTe
1
1
0
0
0
0
0
1 default setting
9.3 Programming the features
When the data transfer of type ‘STATUS’ is selected, the
features SYSTEM CLOCK FREQUENCY and DATA
INPUT FORMAT can be controlled.
System clock frequency: a 2-bit value to select the used
external clock frequency.
Table 7 System clock settings
SC1 SC0
0
0
0
1
1
0
1
1
FUNCTION
512fs
384fs
256fs
not used
Data input format: a 3-bit value to select the data format.
Volume control: a 6-bit value to program the volume
attenuation (VC5 to VC0), 0 to −∞ dB in steps of 1 dB.
Table 9 Volume settings
VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)
000000
0
000001
0
000010
−1
000011
−2
:
:
:
:
:
:
:
111101
−60
111111
−∞
De-emphasis: a 2-bit value to enable the digital
de-emphasis filter.
Table 8 Data input format settings
IF2 IF1 IF0
FUNCTION
0
0
0 I2S bus
0
0
1 LSB-justified, 16 bits
0
1
0 LSB -justified, 18 bits
0
1
1 LSB-justified, 20 bits
1
0
0 MSB-justified
1
0
1 not used
1
1
0 not used
1
1
1 not used
When the data transfer of type ‘DATA’ is selected, the
features VOLUME, DE-EMPHASIS and MUTE can be
controlled.
Table 10 De-emphasis settings
DE1
DE0
FUNCTION
0
0
no de-emphasis
0
1
de-emphasis, 32 kHz
1
0
de-emphasis, 44.1 kHz
1
1
de-emphasis, 48 kHz
Mute: a 1-bit value to enable the digital mute.
Table 11 Mute setting
MT
0
no muting
1
muting
FUNCTION
2000 Jan 10
10
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