ZL30143GGG View Datasheet(PDF) - Microsemi Corporation
Part Name
Description
Manufacturer
ZL30143GGG Datasheet PDF : 4 Pages
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ZL30143
Short Form Data Sheet
1.0 Overview
The ZL30143 System Synchronizer and SETS device is a highly integrated device that provides all of the
functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a
central timing card include:
• Input reference monitoring for both frequency accuracy and phase irregularities
• Automatic input reference selection
• Support of both external timing and line timing modes
• Hitless reference switching
• Wander and jitter filtering
• Master/slave crossover for minimizing phase alignment between redundant timing cards
• Independent derived output timing path for support of the SETS functionality
In a typical application, the main timing path uses DPLL1 to synchronize to either an external BITS source or to a
recovered line timed source. DPLL1 monitors all references and automatically selects the best available reference
based on configurable priority and revertive properties. DPLL1 provides the wander filtering function and the P0
synthesizer generates a jitter filtered clock and frame pulse for the system timing bus which supplies all line cards
with a common timing reference. The APLL is used to generate a reference clock for an Ethernet PHY which can be
used to synchronize remote equipment. A derived output timing path using DPLL2 is available to support the SETS
function. In this case DPLL2 uses a filter above 10 Hz to prevent it from filtering wander.
Figure 2 - Typical Application of the ZL30143
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Microsemi Corporation
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